The project duration is 23 months (February ’15 – December ’16).
The project is structured into nine technical work packages, one specifically looking at exploitation, and one management work package.
The research and development begins with WP2 (Requirements Definition) which elicits the requirements for the TCLS ARM for Space. Requirements covering functionality, performance and interfaces will be developed. A collection of requirements will be devised taking into account information from equipment manufacturers of all Airbus DS sites across Europe.
WP3 (SoC Architectural Definition) aims to provide the architectural concept for TCLS ARM for Space chip. The functional, performance and interface architectural definition for the TCLS ARM for Space chip will be derived from the requirements produced in WP2. From the architecture a corresponding test plan will be derived for the validation of the Triple Core Lockstep and also for the overall SoC demonstrator. The need for radiation protection mechanisms for the ARM Cortex R5 processor core beside the Triple Core Lockstep will be analysed in WP4.
In parallel the architectural design of the Triple Core Lockstep for the ARM Cortex R5 processor core will be performed (WP6). This part of the workpackage, together with WP2, WP3 and WP4 conclude with the Requirements and Architecture Review.
WP7 (Demonstrator Design) focuses on the System-on-Chip (SoC) design for the TCLS ARM for Space demonstrator chip. The VHDL-Verilog mixed RTL code for the demonstrator chip will be designed based on the specifications and architecture developed in WP2 and WP3. The first iteration of the design will be performed using the available single core ARM Cortex R5 processor core, i.e. without the Triple Core Lockstep feature. The advantage is that the complete architecture including all the functions and interfaces can be prepared, verified in simulation and validated on the FPGA demonstration platform, such that the Triple Core Lockstep function can be integrated as soon as available. Also a space mission representative test application will be adapted to the demonstrator (WP8). The results of these workpackages will be reviewed in the SoC Single Core Design Review.
Also the first iteration of the ASIC feasibility study will be performed using the single core processor in order to get the performance and area figures, which can be compared with the TCLS figures in a later step (WP10, WP11).
As soon as the Triple Core Lockstep feature is detailed designed and verified by ARM, the TCLS Readiness review is held. This kicks off the remaining technical workpackages. The feature is integrated into the SoC by replacing the single core by the triple core plus the lockstep logic. A final demonstration on the FPGA platform is carried out. The ASIC feasibility is finally performed using the System-on-Chip including the Triple Lore Lockstep feature and the performance and area figures are derived.