Project Structure

WP1 : Project and Consortium Management

The objectives of WP1 are to coordinate and manage the project work flow and project organisation in order to secure the proper performance of the activities. It will keep all tasks on schedule, ensuring that resources are deployed and adapted, manage risks and eventual recovery actions. It will also facilitate the communication between the team members and handle liaison with the EC management...

WP2 : Requirements Definition

This WP aims in collecting the stakeholders’ needs for a new System-On-Chip. This collection will involve stackholders internal to AIRBUS DS electronic divisions and external (our primes or institutions). Within this WP the needs will be analysed and consolidated in order to generate a consolidated requirement specifications for a new SoC. In addition, requirements will be allocated to the T...

WP3 : SoC Architecture Definition

Based on the TCLS ARM FOR SPACE SoC Requirements Specification gernerated within the WP2, will be analysed and defined an architectural concept of a TCLS ARM-based System-On-Chip. The interfaces will be identified and the peripheral building blocks will be selected. The critical performances will be identified and allocated. In adition will also be identified the reduced architecture of a...

WP4 : Technology Assessment

This WP will analyse the TCLS Technology in regards to the protection mechanisms needed for reliable space applications. It will provide inputs to both the TCLS design and to the SoC design.

WP5 : Exploitation & Final Dissemination

This WP aims at providing a proper dissemination of the final scientific and technical achievements of the TCLS ARM FOR SPACE project. It will promote the final evaluations, will propose clear way forwards and will target in maximizing the exploitation of the results.

WP6 : TCLS Cortex-R5 Design, Verification and Evaluation

The main goals of this WP are to Design, Detail Design, Verify and Assess the Triple Core Lock Step.

WP7 : Demonstrator Design

Based on the outcome of the architecture definition (WP3) this WP has two main objectives. A first one is to provide the design for the demonstrator stream and a second one in providing the design for the SoC ASIC Feasibility study. The demonstrator hardware will be based on a FPGA. For the SoC ASIC Feasibility study stream, RTL code will be implemented within this WP.

WP8 : Test-SW Design

The objective of the WP is to implement a test application that allows demonstrating the basic features of the implemented architecture with focus on dynamic reconfiguration of a failed node.

WP9 : Demonstration

This WP will provide the verification of the behaviour and performance of the Cortex-R5 TCLS concept with real application software. In a first stage, the test plan defined in the WP3 will be executed on the FPGA Hardware and a single core demonstrator.This stage will verify the demonstrator design and will serve as a reference for the next stage. A second stage targets to run the real software...

WP10 : Synthesis for ASIC feasibility study

This WP is intended to prepare the third stream of activities that consists in the Feasibility Study of the implementation of the TCLS ARM for Space on the STM 65nm Rad Hard technology. The synthesis of the TCLS core will be prepared. Constraints for ASIC layout and routing will be also prepared within the frame of this WP.

WP11 : ASIC feasibility study

Within this Work Package, will be performed the feasibility assessment in regard to the processor core, the Triple Cores Lock Step and in regard to the targeted ASIC technology. Trial Placement and layout of the ASIC will be conducted. Area, Power and Clock rate estimation will be performed. This feasibility study will support the selecting the appropriate hardening levels for the system flip-flop...