WP7 : Demonstrator Design

Based on the outcome of the architecture definition (WP3) this WP has two main objectives.
A first one is to provide the design for the demonstrator stream and a second one in providing the design for the SoC ASIC Feasibility study.

The demonstrator hardware will be based on a FPGA.

For the SoC ASIC Feasibility study stream, RTL code will be implemented within this WP.