WP9 : Demonstration

This WP will provide the verification of the behaviour and performance of the Cortex-R5 TCLS concept with real application software.

In a first stage, the test plan defined in the WP3 will be executed on the FPGA Hardware and a single core demonstrator.This stage will verify the demonstrator design and will serve as a reference for the next stage.

A second stage targets to run the real software on the SoC FPGA demonstrator built around the Cortex-R5 TCLS.